Exploring the use of RAM in FPGAs. Taking 4bitX4 as an example, the data bit width is 4 and the depth is 4. The first way is to directly call the 4bitX4 RAM. Write control logic alignment for reading and writing. Compilation under quartus ii, resource consumption. Clock frequency under the 85C model. Clock frequency under the 0C model. The second way is to call the 1bitX4 RAM and instantiate it 4 times. Write control logic alignment for reading and writing. Compilation under quartus ii, resource consumption. Clock frequency under the 85C model. Clock frequency under the 0C model. From the above two cases, the use of the two kinds of RAM, the final use of resources is relatively close, the scheme two is slightly more, and from the comprehensive results of the time series model, the clock frequency of the second scheme is obviously higher than the scheme one. In the case of high speed, it is recommended to use the second option. Similarly, in the case of a wide bit width, it is convenient to use the generated block statement for instantiation to reduce the number of instantiations of the same module on the top layer.
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